1. Field of the Invention
The present invention relates to a charge coupled device (CCD) and, more particularly, to a horizontal charge coupled device (HCCD) which can be adequately applied to multipixel CCD by raising the clock frequency using one-phase clocking.
2. Discussion of Related Art
FIG. 1 shows the layout of a conventional CCD. Referring to FIG. 1, the CCD includes photodiodes PD which converts an optical signal into electrical signal charges, vertical CCDs (VCCD) which are formed in the vertical direction between the photodiodes, and move the signal charges photoelectric converted by the photodiodes, a horizontal CCD (HCCD) which moves the signal charges received from the VCCD in the horizontal direction, and a sensing amplifier SA.
In the CCD constructed as above, the HCCD must read the charges moved from the VCCD in parallel for a short period of time. This requires faster clocking. Accordingly, 2-phase clocking is, generally, applied to the HCCD, different from the VCCD to which 4-phase clocking is carried out.
A conventional HCCD is explained below with reference to the attached drawings. FIG. 2A is a cross-sectional view of a conventional HCCD, and FIG. 2B shows the potential profile of the HCCD. Referring to FIG. 2A, the HCCD includes a P-type well 13 formed in an N-type semiconductor substrate 11, a buried CCD (BCCD) 15 formed in a predetermined region of P-type well 13 and used as a horizontal charge transfer channel, a gate insulating layer 17 formed on BCCD 15, first and second polysilicon gates 19 and 19a repeatedly formed on gate insulating layer 17 and isolated from each other, and a barrier region 21 formed in a predetermined portion of BCCD 15, placed under second polysilicon gate 19a.
As shown in FIG. 2B, the stepped potential well is maintained by barrier region 21 in the conventional HCCD even when an identical clock is applied to the two polysilicon gates. This moves the charges in one direction. Electrons are accumulated in the bottom of the potential well having lower energy level. This operation is described below in detail.
When t=1, charges accumulate in the potential well under the fourth polysilicon gate to which a high voltage is applied. When t=2, a high voltage is applied to the first and second polysilicon gates, to lower the energy level of the region under the first and second polysilicon gates, and a low voltage is applied to the third and fourth polysilicon gates, to increase the energy level of the region under the third and fourth polysilicon gates. Here, the electrons accumulated in the potential well under the fourth polysilicon gate cannot move to the left because of barrier region 21 under the third polysilicon gate.
When the energy level of the region under the fifth and sixth polysilicon gates is gradually lowered to remove the right energy barrier of the region beneath the fourth polysilicon gate, the electrons move to the potential well under the fifth and sixth polysilicon gates whose energy levels are lower. When the energy level of the region under the fifth and sixth polysilicon gates becomes high sufficiently, the stepped potential well is formed again. Accordingly, the electrons accumulated in the potential well under the fourth polysilicon gate move to the potential well under the sixty polysilicon gate.
The above-described CCD uses 2-phase clocking so that it requires two terminals for externally applying clock signals having the phase difference of 180.degree. therebetween. This complicates the configuration of the periphery circuit of the CCD. Furthermore, it is difficult to realize high speed CCDs because of 2-phase clocking.